In an SRAM with conventional six-transistor memory cells (6T cells) based on MOSFET technology, each SRAM cell is coupled between a pair of complementary bit lines (BL), this being known as a folded-BL arrangement. The 6T cell comprises a pair of cross-coupled inverters forming a flip-flop, and transfer transistors controlled by a word line (WL) that respectively connect the flip-flop to the bit lines. The inverters are powered by a supply voltage VDD, and the WL is activated by a VDD-pulse.
There is a move in the industry towards using reduced VDD supply voltages of 0.5 V or less. However, the conventional 6T cell is not well adapted to such a supply voltage reduction. Indeed, the read operation of each cell degrades rapidly as VDD is reduced due to ever-decreasing current-driving capability, in other words the gate-over-drive (GOD) of each transistor in the cell. The GOD is defined as the subtraction of the threshold voltage Vt from the source-gate voltage VGS, and can be expressed as VDD Vt. The threshold voltage Vt of the transistors forming the inverters is generally larger than a typical Vt of 0.4 V to ensure low subthreshold leakage current. Thus there is a speed degradation as the level of VDD supplying the flip-flop and the word line approaches 0.4 V. Furthermore, even larger Vt variations of MOSFETs with the reduction in device dimensions make the situation worse.
To overcome some of these drawbacks, a single-ended 5T cell suitable for an open-BL arrangement has been proposed in the publication by I. Carlson et al. entitled “A high density, low leakage, 5T SRAM for embedded caches”, Proc. 30th European Solid State Circuits Conf. (ESSCIRC), pp. 215-218, 2004, the contents of which is hereby incorporated by reference to the extent permitted by the law. However, such a cell continues to have reduced speed as VDD is reduced. This is because the flip-flop in the cell operates at VDD.
A further problem in existing SRAM cells is the array power dissipation, which is particularly high because operations involve pre-charging the bit lines to the full VDD voltage, leading to a full VDD voltage swing on many of the bit lines. Thus with a typical BL capacitance (CB) of 20-30 fF even for devices as small as 28 nm, the array power dissipation tends to be high. In order to reduce CB by allowing a shorter BL length, a so-called thin-cell has been proposed in a publication by K. Ishibashi and K. Osada entitled “Low Power and Reliable SRAM Memory Cell and Array Design”, Springer, 2012, the contents of which is hereby incorporated by reference to the extent permitted by the law. In such a thin cell, the height of each cell in the bit line direction is lower than its width. However, CB is still relatively large.
There is a need in the art for an SRAM that addresses one or more of the above problems.